1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including transistor elements that comprise a high-k metal gate electrode structure formed in an early process stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a great number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Currently, a plurality of process technologies are practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a planar transistor architecture, the distance between the source and drain regions, which is also referred to as channel length.
Presently, the vast majority of integrated circuits are formed on the basis of silicon due to its substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the experience gathered during the past 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a base material for gate insulation layers that separate the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by, among other things, the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length for a planar transistor configuration requires an increased capacitive coupling in combination with sophisticated lateral and vertical dopant profiles in the drain and source regions to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled planar transistor devices with a relatively low supply voltage and, thus, reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly reduced to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although usage of high speed transistor elements having an extremely short channel may typically be restricted to high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by the direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of circuits.
For this reason, new strategies have been developed in overcoming the limitations imposed by high leakage currents of extremely thin silicon oxide-based gate insulation layers. One very promising approach is the replacement of the conventional dielectric materials, at least partially, by dielectric materials having a dielectric constant that is significantly greater than the dielectric constant of silicon dioxide-based materials. For example, dielectric materials, also referred to as high-k dielectric materials, with a dielectric constant of 10.0 and significantly higher may be used, for instance in the form of hafnium oxide, zirconium oxide and the like. In addition to providing a high-k dielectric material in the gate insulation layers, appropriate metal-containing materials also may have to be incorporated since the required work function values for P-channel transistors and N-channel transistors may not be obtained on the basis of standard polysilicon gate materials. To this end, appropriate metal-containing materials may be provided so as to cover the sensitive high-k dielectric materials and act as a source for incorporating an appropriate metal species, such as lanthanum, aluminum and the like, in order to appropriately adjust the work function for N-channel transistors and P-channel transistors, respectively. Furthermore, due to the presence of a metal-containing conductive material, the generation of a depletion zone, as may typically occur in polysilicon-based electrode materials, may be substantially avoided. The process of fabricating a sophisticated gate electrode structure on the basis of a high-k dielectric material may require a moderately complex process sequence due to, for instance, the adjustment of an appropriate work function for the transistors of different conductivity type and the fact that high-k dielectric materials may typically be very sensitive when exposed to certain process conditions, such as high temperatures in the presence of oxygen and the like. Therefore, different approaches have been developed, such as providing the high-k dielectric material at an early manufacturing stage and processing the semiconductor devices with a high degree of compatibility with standard process techniques, wherein the typical electrode material polysilicon may be replaced in a very advanced manufacturing stage with appropriate metals for adjusting the work function of the different transistors and for providing a highly conductive electrode metal. While this approach may provide superior uniformity of the work function and thus of the threshold voltage of the transistors, since the actual adjustment of the work function may be accomplished after any high temperature processes, a complex process sequence for providing the different work function metals in combination with the electrode metal may be required. In other very promising approaches, the sophisticated gate electrode structures may be formed in an early manufacturing stage, while the further processing may be based on the plurality of well-established process strategies. In this case, the high-k dielectric material and any metal species for adjusting the work function may be provided prior to or upon patterning the gate electrode stack, which may comprise well-established materials, such as silicon and silicon/germanium, thereby enabling the further processing on the basis of well-established process techniques. On the other hand, the gate electrode stack and, in particular, the sensitive high-k dielectric materials in combination with any metal-containing cap layers may remain reliably confined by appropriate materials throughout the entire processing of the semiconductor device.
Further concepts for enhancing performance of transistors have been developed by providing a plurality of strain-inducing mechanisms in order to increase the charge carrier mobility in the channel regions of the various transistors. It is well known that charge carrier mobility in silicon may be efficiently increased by applying certain strain components, such as tensile and compressive strain for N-channel transistors and P-channel transistors, respectively, so that superior transistor performance may be obtained for an otherwise identical transistor configuration compared to non-strained silicon materials. For instance, efficient strain-inducing mechanisms may be implemented by incorporating a strained semiconductor material in the drain and source regions of transistors, for instance in the form of a silicon/germanium alloy, a silicon/carbon alloy and the like, wherein the lattice mismatch between the semiconductor alloy and the silicon base material may result in a tensile or compressive state, which in turn may induce a desired type of strain in the channel region of the transistor. Other efficient strain-inducing mechanisms are well established in which a highly stressed dielectric material may be positioned in close proximity to the transistor, thereby also inducing a certain type of strain in the channel region.
Although the approach of providing a sophisticated high-k metal gate electrode structure in an early manufacturing stage, possibly in combination with additional strain-inducing mechanisms, may have the potential of providing extremely powerful semiconductor devices, such as CPUs, storage devices, systems on a chip (SOC) and the like, conventional approaches may still suffer from process non-uniformities, as will be described with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, such as a silicon substrate, in combination with a semiconductor layer 102, such as a silicon layer or a semiconductor material comprising a significant amount of silicon. In the manufacturing stage shown, the semiconductor device 100 further comprises transistors 150A, 150B in an early manufacturing stage which may be formed in and above an active region 102A and 102B, respectively. An active region is to be understood as a semiconductor region in the layer 102 in which PN junctions for one or more transistors are to be formed. An isolation structure 102C, such as a trench isolation, is provided in the semiconductor layer 102 and may laterally delineate active regions, such as the regions 102A, 102B. Furthermore, a plurality of gate electrode structures 160A, 160B and 160C may be formed above the semiconductor layer 102. In FIG. 1a, the gate electrode structures 160A, 160B are illustrated at a cross-section in which the gate electrode structures 160A, 160B are formed on the active regions 102A and 102B, respectively, wherein it should be appreciated that these gate electrode structures may extend beyond the corresponding active region, if required, and may thus be formed above a corresponding isolation region. For example, the gate electrode structure 160C may represent a corresponding portion of a gate electrode structure or may represent a conductive line or any other circuit element, such as a resistive structure and the like, which may have a similar configuration as the gate electrode structures 160A, 160B. As previously discussed, the gate electrode structures may comprise a gate insulation layer 161 formed on the active region 102A and 102B, respectively, and may comprise a high-k dielectric material, such as hafnium oxide-based materials and the like. It should be appreciated that, frequently, the gate insulation layer 161 may additionally comprise a conventional dielectric material, such as a silicon oxide-based material, however, with a significantly reduced thickness of approximately 0.8 nm and less. Consequently, in total, the gate insulation layer 161 may have a thickness of 1.5 nm and more, while still providing an oxide equivalent thickness that may be 1 nm and less, while leakage currents may be significantly less compared to a conventional extremely thin silicon oxide-based material. Moreover, a metal-containing material may be formed on the gate insulation layer 161 and may have a different composition for transistors of different conductivity type. For example, a conductive cap layer 162A may be provided in the gate electrode structure 160A including a work function adjusting species for the transistor 150A, while a conductive cap layer 162B including a work function species for the transistor 150B may be applied in the gate electrode structure 160B. Typically, the gate electrode structure 160C may have one of the layers 162A, 162B. Moreover, an electrode material 163, such as silicon, silicon/germanium and the like, may be formed above the conductive cap layers 162A, 162B, respectively, followed by a dielectric cap layer 164, which is typically comprised of silicon nitride.
Furthermore, a sidewall spacer structure 165, which may comprise a liner material 165A in combination with a spacer element 165B may be provided so as to protect the sidewalls of the electrode material 163 and in particular of the sensitive materials 162A, 161. The liner 165A and the spacer element 165B may typically be comprised of silicon nitride. As illustrated, above the active region 102b and the gate electrode structure 160B, the materials 165A, 165B may be in the form of non-patterned layers in order to provide a growth mask for forming a strain-inducing semiconductor material 151 in the active region 102A so as to increase the charge carrier mobility in a channel region 152 of the transistor 150A. Moreover, the active region 102A may comprise a semiconductor alloy 152A in the channel region, for instance a silicon/germanium alloy, in order to adjust the band gap offset of the channel region, thereby obtaining a desired threshold voltage in combination with the materials 161 and 162A for the transistor 150A.
As previously discussed, the semiconductor alloy 151, for instance provided in the form of a silicon/germanium alloy, may have a strained state and may thus induce a desired strain in the channel region 152. For instance, silicon/germanium may represent a very efficient strain-inducing source for P-channel transistors.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following conventional process strategies. After forming the isolation region 102C and thus delineating the active regions 102A, 102B, the material layer 152A may be formed selectively in the active region 102A. Next, appropriate materials for the gate insulation layer 161 and one of the layers 162A and 162B may be formed by any appropriate deposition technique. Thereafter, the conductive cap material may be appropriately patterned and the other one of the layers 162A, 162B is deposited, possibly followed by any heat treatments in order to appropriately diffuse a work function adjusting species towards the gate insulation layer 161. Prior to or after the corresponding adjustment of the work function, the electrode material 163, for instance in the form of silicon, may be deposited on the basis of well-established deposition techniques, followed by the deposition of the dielectric cap layer 164. Furthermore, additional materials, such as hard mask materials and the like, may be provided if required and thereafter a sophisticated lithography process and an anisotropic etch sequence may be performed in order to obtain the gate electrode structures 160A, 160B, 160C. During the patterning process, the dielectric cap layer 164 may thus provide superior efficiency of the patterning process and may also be used during the subsequent processing so as to encapsulate the electrode material 163 and the materials 162A, 161. As previously discussed, in sophisticated applications, a length of the gate electrode structures 160A, 160B, 160C, i.e., in FIG. 1a, a horizontal extension of the electrode material 163, may be 50 nm and less. Next, the materials 165A, 165B may be formed, for instance, by thermally activated chemical vapor deposition (CVD) techniques, plasma enhanced CVD techniques and the like, in order to form, in particular, the liner material 165A as a very dense silicon nitride material so as to reliably confine the sidewalls of the gate electrode structures. Thereafter, an etch mask may be provided to cover the transistor 150B in order to form the spacer elements 165B and possibly etch into the active region 102A in order to form corresponding cavities therein. During the corresponding etch process, the spacer structure 165 may substantially determine a lateral offset of the corresponding cavities with respect to the channel region 152. Next, a selective epitaxial growth process is performed in order to grow the strain-inducing semiconductor material 151. During a selective epitaxial growth process, process parameters are adjusted such that a significant material deposition on dielectric surface areas, such as the cap layers 164, the material 165B and the isolation region 102C, is substantially suppressed.
FIG. 1b schematically illustrates the semiconductor device 100 in a manufacturing stage in which an etch mask 103 covers the active region 102A and possibly the isolation region 102C, while exposing the gate electrode structure 160B and the active region 102B. Moreover, an etch process 104 is applied so as to obtain the spacer structure 165 on sidewalls of the gate electrode structure 160B. For this purpose, well-established plasma assisted etch recipes are applied. It should be appreciated that, during the etch process 104, a certain amount of material erosion in the active region 102B or material modification may occur, depending on the etch chemistry used. For example, plasma assisted etch recipes for removing silicon nitride may exhibit a self-limiting behavior when etching a silicon material, which may be caused by the generation of silicon dioxide, which may then act as an efficient etch stop material.
Thereafter, the etch mask 103 may be removed and thus the gate electrode structures 160A, 160B, 160C may have a substantially similar configuration, i.e., may comprise the sidewall spacer structure 165, which may be used as an offset spacer structure for controlling a subsequent implantation sequence for introducing dopant species so as to form drain and source extension regions and halo regions, i.e., counter-doped regions, in order to obtain the required complex dopant profile for adjusting the overall transistor characteristics. During the further processing, the dielectric cap layers 164 may also have to be removed, which may, however, have a significant influence on the resulting device topography and thus on the resulting transistor characteristics. For instance, upon removing the dielectric cap material 164, etch chemistries, such as hot phosphoric acid, are typically applied which, however, may exhibit a significant lateral etch rate, thereby causing a significant degree of material erosion of the spacer structure 165. For this reason, the spacer structure 165 is protected by providing a sacrificial oxide spacer element having a high etch resistivity with respect to hot phosphoric acid.
FIG. 1c schematically illustrates the semiconductor device 100 with an oxide spacer layer 166, which may be etched during an etch process 105 in order to form sacrificial oxide spacers 166S on the sidewall spacer structure 165. Consequently, during the etch process 105, a certain degree of material erosion 105R may occur in the isolation structure 102C due to a certain required overetch time during which oxide material of the isolation structure 102C is removed.
FIG. 1d schematically illustrates the device 100 when exposed to a further etch process 106 for removing the dielectric cap material 164 (FIG. 1c) on the basis of hot phosphoric acid. As discussed above, during the etch process 106, the silicon nitride spacer structure 165 is protected by the sacrificial spacer elements 166S.
FIG. 1e schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, the sacrificial sidewall spacers 166s (FIG. 1d) are removed, which may be accomplished on the basis of diluted hydrofluoric acid (HF), which, however, may also remove a further portion of the isolation structure 102C, thereby increasing the recess 105R. Consequently, after the removal of the dielectric cap layer 164
(FIG. 1c), a pronounced surface topography in the form of the recess 105R may be created, which may have a significant influence on the further processing.
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a further sidewall spacer structure 155 is formed adjacent to the spacer structure 165 (FIG. 1e) and is typically comprised of silicon nitride, possibly in combination with a silicon dioxide etch stop liner (not shown). Furthermore, drain and source regions 153 are formed in the active regions 102A, 102B corresponding to the conductivity type of the transistors 150A, 150B. Furthermore, metal silicide regions 154 are formed in the drain and source regions 153 and metal silicide regions 167 are provided in the gate electrode structures 160A, 160B, 160C. Additionally, a dielectric layer 120, which may have a high internal stress level, is formed above the active regions 102A, 102B, the isolation region 102C and above the gate electrode structures 160A, 160B, 160C. As previously explained, a highly stressed dielectric material provided in the vicinity of a channel region of a transistor may represent an efficient strain-inducing mechanism, wherein the resulting amount of transistor performance enhancement may strongly depend on the internal stress level of the layer 120 and the amount of highly stressed material positioned in close proximity to the channel region 152, which in turn may thus depend on the thickness of the layer 120. Consequently, in view of enhancing transistor performance, an increased layer thickness is highly desirable for the layer 120, which, however, may be restricted by the pronounced surface topography, in particular in the isolation region 102C. That is, in device areas comprising closely spaced gate electrode structures extending along an isolation region, such as the region 102C, the pronounced recessing caused by the previous processing may additionally increase the resulting aspect ratio that is “seen” during the deposition of the material 120. Consequently, in view of the pronounced recessing of the isolation structure 102C, a reduced thickness of the layer 120 may have to be provided in order to avoid deposition-related irregularities, which may otherwise result in significant yield losses during the further processing, for instance when forming contact elements and the like.
The semiconductor device 100 as illustrated in FIG. 1f may be formed in accordance with the following process techniques. The spacer structure 155 is typically formed by depositing a silicon nitride material, possibly in combination with a silicon dioxide etch stop liner, and patterning the silicon nitride layer so as to obtain a spacer element, as shown. Prior to and after forming the sidewall spacer structure 155, implantation processes are performed in order to introduce dopant species, thereby forming the drain and source regions 153. After any anneal processes in which the final dopant profile may be established, further cleaning processes are performed in order to prepare the exposed semiconductor surface areas for forming the metal silicide regions 154, 167. Typically, during any such cleaning processes, a further recessing in the isolation region 102C may be caused, thereby further contributing to the very pronounced surface topography. Thereafter, a silicidation process may be performed wherein the spacer structure 155 may substantially determine the lateral offset of the metal silicide regions 154 with respect to the channel region 152. Next, the dielectric material 120 is deposited, wherein, depending on the process requirements, a complex deposition and patterning sequence may also have to be applied when dielectric materials of different internal stress levels are to be provided above the transistor 150A and the transistor 150B. During the corresponding deposition process or processes, the pronounced surface topography has to be taken into consideration, as discussed above, thereby possibly reducing the efficiency of the strain-inducing effect of the dielectric material 120.
Consequently, although the conventional approach may provide high performance transistors on the basis of the high-k metal gate electrode structures 160A, 160B, 160C, the pronounced surface topography in the isolation region 102C mainly caused by the removal of the dielectric cap layer 164, results in reduced device performance and increased yield loss.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.